application note semiconductor group 302 the digital display processor sda 9280 with integrated 9-bit triple d/a converter for enhanced tv applications abstract the described single ic performs processing and a 9-bit da conversion of video component signals. it accepts multiple input data formats and improves picture quality by luminance peaking filtering, digital chrominance transition improvement and oversampling techniques. display format control (4:3, 16:9, ) is realized by time compression or expansion. summary cost-reduction of tv systems by reduction of the analog application requirements, coupled with an improvement of the picture quality can be achieved by extended digital signal processing. some of this dsp possibilities, being combined with on-chip d/a conversion have been implemented in the presented display processor in a 1- m m cmos technology with two layer metallization. the chip has an area of 50.17 mm 2 , containing 179397 transistors. most of the used registers are of a dynamic 8-transistor type. the ic is completely controlled by i 2 c bus. the possible input data formats are 4:1:1, 4:2:2 parallel, ccir 656 and 4:4:4 with 8-bit word length. the maximal input clock frequency is 30 mhz. for internal processing the chrominance data of other formats are interpolated to the 4:4:4 parallel format by two interpolation filters (interpolator 1). each filter performs a two fold oversampling. a luminance peaking filter improves the over all frequency response of the luminance channel. it consists of three filters working in parallel. they have lowpass, bandpass and highpass characteristics and are separately programmable. an amplification of up to 14 db at the half of the sample frequency is available. a new digital algorithm has been implemented to improve transitions of the chrominance signals, resulting in a better picture sharpness. a slow change from one color to another because of small chrominance bandwidth is replaced by a steep transition. two bandwidth optimized paths are implemented to detect the position of a color transition in the incoming chrominance signals. the better suited path is chosen automatically. the sensitivity of this digital color transition improvement (dcti) circuit is programmable. a compander for time-compression or time-expansion enables a display of signals having different display formats with correct geometric proportions, e.g. 4:3 signals on 16:9 screens or 16:9 signals on 4:3 screens. the horizontal compression or expansion of the video signals is performed by raising or reducing the sample frequency. the data is written into a memory using the system clock and read with a clock of higher or lower frequency. the compander is a fifo memory with a storage capacity of 28 x 188 = 5264 bits implemented as a two-pointer controlled dram with dynamic three-transistor memory cells. the operation frequency of the compander is reduced to maximal 10 mhz by 4-bit parallel-conversion of the serial input write data and parallel-serial-conversion of the output read data.
application note semiconductor group 303 a two fold oversampling filter (interpolator 2) transforms the internal used data format 4:4:4 to 8:8:8 before da conversion in order to reduce the requirements for external analog postfiltering. a pipelined carry save architecture is used for the digital filter. carry-select vector merging adders (vma) add the sum and carry word vectors for each sample. the filter is of a halfband type. a two phase processing structure is realized. the filter consists of a simple delay path and a filter path, both working at half the oversampling frequency. the output samples are taken alternating from the delay path and the filter path. the interpolator 2 has a steep transition at half the sampling frequency, an out of band rejection of more than 30 db, a flat frequency response in the pass band and low overshooting in the time domain. the maximal output clock frequency is 80 mhz. three different values can be inserted into the video signal: black level, a colored background area and an arbitrary colored pattern. all insertions are performed after oversampling resulting in sharp transitions without overshooting. to avoid a deterioration of the signal-to-noise ratio caused by word length reduction a first order noise shaper is implemented before d/a conversion. the architecture of the triple d/a converter has been chosen to be a mixture of binary weighted current cells and monotonic decoding of unity cells: the 5 msbs are created in a linear array of 31 unit cells delivering a 16 x lsb current. the 4 lsbs are added as binary weighted current sources. the measurements of the triple d/a converter show a total linearity error of less than 0.5 lsb and a s/n ratio of 50 db (rms-rms) in a 25-mhz band, at an analog frequency of 12 mhz and a operation frequency of 108 mhz. an internal pll supplies the clock signals needed for all operation modes. it is designed with a differential 5-stage ring oscillator (vco), a digital type-4 phase detector providing short anti backlash impulses and a single-ended external loop filter. the output frequency of the pll is programmable in a wide range. the clock system is divided into six subsystems, each generating a four-phase non-overlapping clock. two subsystems are used for the synchronization of the input data. the demultiplexing of the various input data formats especially for 'zoom'-mode applications raise the necessity of the third clock subsystem. the further clock systems are used for the system clock, the compander reading clock and the oversampling clock. all functions have been verified with oversampling clock frequencies in excess 108 mhz at typical operation conditions.
application note semiconductor group 304 chip microphotograph
application note semiconductor group 305 block diagram
|
